1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor device and, more particularly, to a stack package having a plurality of unit packages that may be inserted into a receiving substrate to be stacked and electrically connected to each other, and a semiconductor module that may implement the same.
2. Description of the Related Art
The electronic industry may seek to provide products having (for example) characteristics of light-weight, miniaturization, high speed, multifunction, high performance, high reliability and low production cost. Packaging may be one technology area that may enable design of such a product. One packaging technique may provide a chip scale package (CSP), which may have a size comparable to a semiconductor chip.
Various technologies may attempt to provide a greater number of cells in the limited space of a semiconductor chip to increase the capacity of a semiconductor chip, but such technologies are not without shortcomings. For example, such technologies may involve fine line-widths and/or a substantial development time. Accordingly, some approaches may attempt to increase integration by stacking semiconductor chips and/or semiconductor packages to form a stack package.
One stack package may be manufactured by stacking a plurality of semiconductor chips. However, the chip stacking techniques may suffer from a decreased yield. For example, a stack chip package may be classified as a failed product if it includes a defective semiconductor chip. Here, repair work may not be possible.
Another stack package may be manufactured by stacking a plurality of unit packages. On the one hand, the unit package stacking technique may result in a stack package that is thicker than one manufactured by stacking chips. On the other hand, yield may be improved because (for example) the quality of a unit package may be verified prior to the stacking process. Additionally, the increase in thickness may be reduced by using a chip scale package as the unit package.
FIG. 1 illustrates a conventional stack package that may implement a chip scale package as a unit package. Here, the stack package 10 may include a stack of four unit packages 20.
Each of the unit package 20 may be a chip scale package. A semiconductor chip 24 may be mounted on the upper surface of a substrate 22. Conductive bumps 26 may be provided on the lower surface of the substrate 22. Connecting pads 28 may be provided on the upper surface of the substrate 22. The connecting pads 28 may be located over the conductive bumps 26. Electrical connections between the semiconductor chip 24 and the substrate 22 may be sealed with a molding resin (not shown). The molding resin may be selected from the epoxy family, for example.
Stacking the unit packages 20 may involve mounting an upper unit package on a lower unit package, and applying heat to melt the conductive bumps 26. When melted and then cooled, the conductive bumps 26 of an upper unit package may be fixed to the connecting pads 28 of a lower unit package. This stacking process (inclusive of the heat application technique) may be repeated to complete the stack package 10.
Heat over 200° C. may be applied to melt the conductive bumps 26. The application of heat may cause thermal stresses in the components of the stack package 10. Such thermal stresses may damage the components.
For example, thermal stresses may cause defects, such as splitting of conductive bumps and/or short circuits between adjacent conductive bumps. Package defects may occur more frequently as the number of unit packages in the stack increases.
Additionally, components of a stack package such as substrates, molding resin, and semiconductor chips may have different coefficients of thermal expansion. Thus, during processes that may involve the application of heat (e.g., the stacking of unit packages), substrate warpage may occur. Substrate warpage may cause defects. For example, conductive bumps may become disconnected from a lower substrate.
A stack package may be subjected to test processes that may include (for example) an appearance inspection. A stack package identified as incorrectly assembled and/or including a defective unit package may be repaired by a process that may involve re-assembly of the stack package. If the stack package is identified as including a defective unit package, then the repair process may involve replacing the defective unit package with another unit package. In the repair process, heat may be applied to the defective unit package, as well as other component parts of the stack package. Accordingly, the repair process may cause the aforementioned defects.
In addition, the unit package may have a structure that exposes a semiconductor chip. Thus, the semiconductor chip may be susceptible to damage from external forces.
By way of example only, the stack package may be installed on a motherboard or, as shown in FIG. 2, on a module substrate 60 as a component part of a semiconductor module 50. The stack packages 10 may be installed on both sides of the module substrate 60.
The semiconductor module 50 may suffer from thermal stresses as described above, because the stack packages 10 may be installed on the module substrate 60 by a process that may involve the application of heat.